Adaptive IDDQ: How to Set an IDDQ Limit for any Device Under Test

The combination of deep sub-micron technologies together with System on Chip complexity has brought the Device Under Test (DUT) Quiescent Supply Current (IDDQ ) into the Milliamps (mA) range. This IDDQ level, modulated by Electrical Parameters and Critical Dimensions Process spreads , makes almost impossible to detect the small current increase caused by the presence of a defect into the DUT. The integration of a limited size IDDQ cell into the DUT, combined with Automatic Test Equipment (ATE) measurements and calculations allows to define an IDDQ limit for every DUT during Electrical Wafer Sort (EWS) revitalizing a powerful way to prevent defective chips can reach the application field. In the today mass production CMOS technologies (.18micron and .13micron) is quite common to deal with high levels of Quiescent Supply Current, making very critical and unsafe the IDDQ testing. If IDDQg is defined as the” Quiescent Current associated to a Good DUT” and IDDQt as the “Quiescent Current Threshold “ to be used as limit by the ATE, in the relationship: IDDQd=IDDQg+Isc>IDDQt (1) the smaller the level of Isc (extra current due a single defect into the chip) the highest the efficiency to capture and reject Defective devices. Unfortunately IDDQg is heavily affected by Process Variations and during mass production IDDQg can easily move one order of magnitude, (500uA to 5mA) while Isc stays in the range of few hundreds of micro-Amps. The use of differential IDDQ test method can only mitigate the described problem. A more accurate value for IDDQt can be set deriving it directly for every DUT. The basic simple IDDQ cell, embedding two arrays of N and P Mos (fig1 and fig.2), is integrated into the chip and made reachable by EWS needle probes thanks to the addition of only two pads. The linkage between the (normalized) Isub (subthreshold current) and the total number of N and P Mos devices (with their channel widths W) in Off conduction state: ΣWNoff, ΣWPoff (during the IDDQQ test at Vdd1 voltage supply) is expressed by IDDQg(Vdd1)=IsubN(Vdd1)· ΣWNoff+IsubP(Vdd1)· ΣWPoff (2) To solve the (2), finding the unknown : ΣWNoff, ΣWPoff (which will become proprietary number of the DUT in the specific IDDQ test file) at least one Good sample has to be identified and its IsubN and IsubP measured on its IDDQ cell in the most accurate possible way (ATE to use Precision Measurement Unit or Dedicated High Resolution Hardware) . Doing that at two different DUT Supply voltages will provide the Isub and IDDQg constants to solve the system of equations based on (2). The now defined ΣWNoff, ΣWPoff stored into ATE memory will be applied, during EWS, in combination with IsubN, IsubP measured for every DUT.During EWS the ATE will compute IDDQg as DUT is a Good device. The IDDQt limit will therefore be set having reduced the huge IDDQg noise caused by Process Parameters Variations. IDDQt=IDDQg+Isc<IDDQd (3) Into (3) the Isc will be close to 170uA for a (typical) .18micron technology to 250uA in a .13 one (@25°C). The IDDQ cell inserted into the Digital Libraries of every new CMOS technology, is integrated into chip layout with negligible impact on die area and pads count. Fig 1: Gate, Source and Substrate connected at DUT Ground, Drain connected at Pad 1 Fig 2: Gate, Source and Substrate connected at Pad 2, Drain connected at DUT Ground Proceedings of the Eighth IEEE International On-Line Testing Workshop (IOLTW’02) 0-7695-1641-6/02 $17.00 © 2002 IEEE